Udemy – SystemVerilog/UVM for ASIC/SoC Verification Part 1 2024-8

Published on: 2024-10-27 20:32:28

Categories: 28

Description

SystemVerilog/UVM for ASIC/SoC Verification Course Part 1. Are you ready to enter the world of SystemVerilog and unlock its potential for industrial-scale design and verification? Designed specifically by the Quant Semicon team, our comprehensive course is for beginners and advanced learners who want to master SystemVerilog (SV) and its Object Oriented Programming (OOP) concepts. With a hands-on approach and real-world examples, this course takes you from SV basics to advanced applications, preparing you for the challenges of the semiconductor industry. By the end of this course, you will have a strong foundation in VLSI verification principles and hands-on experience, and be ready to tackle complex verification challenges in industry. Whether you’re a student preparing for a career in the semiconductor industry or a professional looking to sharpen your skills, this course provides a complete, structured path to mastering SystemVerilog. Join us and take the first step to becoming a SystemVerilog expert!

What you will learn in the SystemVerilog/UVM for ASIC/SoC Verification Part 1 course

Learn the basics of SystemVerilog, different data types, procedural blocks and control flow structures.
Explore how to facilitate reusable and scalable testbenches with OOP concepts.
Learn how to use SystemVerilog interfaces to simplify the connection between design modules.
Learn how to verify correct master-slave interaction and signal behavior in APB transactions.
Learn the basics of UVM
On-chip design verification concepts

This course is suitable for people who

Students: Electronics, Microelectronics, VLSI, Embedded
Employed professionals: VLSI design specialist, verification engineers, verification supervisors