Synopsys Synplify with Design Planner L-2016.03-SP1

Published on: 2022-10-16 18:41:53

Categories: 12

Description

Synopsys Synplify software is the industry standard for producing high-performance, cost-effective FPGA designs. Synplify supports the latest VHDL and Verilog language structures, including SystemVerilog and VHDL-2008. The software also supports FPGA architecture by a variety of FPGA vendors including Altera, Achronix, Lattice, Microsemi and Xilinx. Synplify software uses an easy interface and is capable of performing add-ons and visual analysis of HDL code.

Features and Features of Synopsys Synplify:

Auto-compile incremental flow points 4x faster
Acceleration runtime with support for up to 4 processors
TCL script support for automated flow and adjustable blending, debugging and reporting
Optimal area and time results using FPGA from Achronix, Altera, Lattice, Microsemi, Xilinx
Manage multiple design implementations for large design team projects
Custom mapping software for each FPGA device ensures optimal execution
Conclusions Automatic memory and DSP execution of the plan with the desired region provides the power and quality of the results time.
FSM extraction, optimization and debugging with user control
Detectable and verifiable flow using control that limits the optimization of the combination.
Integration with VCS simulation for simulation data analysis
Generates high quality data to drive power optimization
ASIC language tool and SDC compatibility constraint
Process management interface to monitor design progress and errors
Synchronize geographical distribution / projects against multiple devices

Click here for full Synopsys Synplify information.

required system

System Requirements: PC / Linux
Supported Operating Systems: Windows 7even / 8.x | RHEL 5-7 (Red Hat Enterprise Linux) / SLES 11 or 12 (SUSE Linux Enterprise Server)