Synopsys IC Compiler II vP-2019.03-SP5

Descriptions

IC Compiler II is the industry leading place and route solution that delivers best-in-class quality-of-results (QoR) for next generation designs across all market verticals and process technologies, while enabling unprecedented productivity. IC Compiler II includes innovative for flat and hierarchical design planning, early design exploration, congestion aware placement and optimization, clock tree synthesis, advanced node routing convergence, manufacturing compliance, and signoff closure. IC Compiler II is specifically architected to address aggressive performance, power, area (PPA), and time-to-market pressures of leading edge designs. Key technologies include a pervasively parallel optimization framework, multi-objective global placement, routing driven placement optimization, full flow Arc based concurrent clock and data optimization, total power optimization, multi-pattern and FinFET aware flow and machine learning (ML) driven optimization for fast and predictive design closure. Advanced Fusion technologies offer signoff IR drop driven optimization, PrimeTime delay calculation within IC Compiler II, exhaustive path based analysis (PBA) and signoff ECO within place and route for unmatched QoR and design convergence.

Features of Synopsys IC Compiler :

• Hierarchical Infrastructure: Enables massive parallelism, scalable data access, and efficient modification of large designs.
• Multi-Corner and Multi-Mode (MCMM) Architecture: Supports analysis and optimization across multiple modes and corners.
• Next-Generation Design Planning: Combines novel, adaptive-abstraction, and parallel computing techniques for efficient floorplanning and exploration.
• Global Optimization: Enables optimization of large chunks of logic simultaneously, reducing the risk of local minima and improving design quality.
• Clock Synthesis: Supports advanced clock synthesis and optimization, including concurrent clock-and-data (CCD) optimization.
• Physical Synthesis and Optimization: Includes techniques for congestion-aware placement, pin assignment, and optimization, as well as support for complex design styles and flows.
• Timing Engine: Architected for modern designs with multiple modes and corners, featuring a single, cross-flow implementation timer

System Requirements

Operating System

linux

Picture

Installation guide

Read the Readme.txt file in the crack folder.

Download Link

Download Part 1 – 1 GB

Download Part 2 – 562 MB

Password file(s): www.abc.com

Size

1.5 MB